// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : WRADDR_GEN_CTRL.v
// Module Name  : ctrl
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module ctrl(
    input CLK,
    input RST_N,
    input [4:0] SRAM_NUM,
    input SOP,
    input EOP,
    input VLD,
    input [35:0] DATA,
    input [12:0] SRAM_ADDR,
    output reg [4:0] SRAM_NUM_O,
    output reg SOP_O,
    output reg EOP_O,
    output reg VLD_O,
    output reg [35:0] DATA_O,
    output reg [12:0] SRAM_ADDR_O
);

//localparam count_max = 8192-SRAM_ADDR-1;

logic [12:0] count;
logic [12:0] addr;
logic [0:0] count_tag;

always@(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        count_tag<=1'b0;
        count<=13'd0;
    end
    else begin
            if(VLD) begin
                if(count==8191-SRAM_ADDR) begin
                    count<=13'd0;
                    count_tag<=1'b1; end
                else begin
                    count<=count+1;
                    count_tag<=count_tag;
                    end
            end
        end
    end

assign SRAM_ADDR_O=(!count_tag)? SRAM_ADDR+count:count;
always@(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        SRAM_NUM_O<=5'd0;
        EOP_O<=1'b0;
        SOP_O<=1'b0;
        VLD_O<=1'b0;
        DATA_O<=36'd0;
    end
    else begin
        SRAM_NUM_O<=SRAM_NUM;
        EOP_O<=EOP;
        SOP_O<=SOP;
        VLD_O<=VLD;
        DATA_O<=DATA;
    end    
end

endmodule

